![]() But high bandwidth needs and negative interference (e.g.No cache coherence problem (and hence no false sharing either).Low-latency sharing and prefetching across processors.Bus-snooping mechanisms used to address the cache coherency problem.Also attractive for high throughput servers.Building blocks for larger parallel systems (MPPs, clusters).Commonly called: Symmetric Memory Multiprocessors (SMPs).Symmetric access to all of main memory from any processor.A number of processors (commonly 2-4) in a single node share physical memory via system bus or point-to-point interconnects (e.g.Uniform Memory Access (UMA) Multiprocessors Shared Memory Multiprocessors Variations Symmetric Memory Multiprocessors (SMPs) UMA (interleaved) Second-level $ UMA e.g CMPs Bus or point-to-point interconnects Or SMP nodes Scalable Distributed Shared Memory UMA NUMA Scalable network p-to-p or MIN Cache coherence achieved by directory-based methods.Most popular design to build scalable systems (MPPs).Shared memory is physically distributed locally among processors (nodes).Non-uniform Memory Access (NUMA) or distributed memory Multiprocessors:.Symmetric Memory Multiprocessors (SMPs).Bus-based shared memory multiprocessors.Can be further divided into three types:.All processors have equal access to all memory addresses.Uniform Memory Access (UMA) Multiprocessors :.Shared Memory Multiprocessors Variations The focus here is on supporting a consistent or coherent shared address space.Can offer very high performance since no OS involvement necessary.Message passing using shared memory buffers:.Address translation and protection in hardware (hardware SAS).Pr ogramming models Message passing Compilation Multipr ogramming Communication abstraction or library User/system boundary Shar ed addr ess space Operating systems support Har dwar e/softwar e boundary Communication har dwar e Physical communication medium Shared Memory Multiprocessors: Support of Programming Models Caches in the extended memory hierarchy may have multiple inconsistent copies of the same data leading to data consistency or cache coherence problem that have to addressed by hardware architecture. ![]()
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